Q100规范基于32位Arm® Cortex®-M4F和Cortex-M0+内核的MCU.MCU工作电压2.7V到5.5V,HSRUN模式的工作温度为-40℃到105℃,RUN模式的工作温度为-40℃到 150℃.HSRUN模式的CPU支持高达112MHz，具有1.25 Dhrystone
MIPS per MHz.器件集成了数字信号处理器(DSP)，可配置嵌套矢量中断控制器(NVIC)以及单精度浮点单元(FPU).器件集成了带ECC的多达256KB SRAM，多达
4KB FlexRAM，多达4kB代码缓冲器，以最小化性能对存储器存储的性能冲击，并支持有HyperBus™的QuadSPI.功率管理控制器(PMIC)具有多种降功耗模式:HSRUN, RUN, STOP, VLPR以及VLPS.主要用在通用汽车和高可靠性工业应用.中电网为您整理如下详细资料，本文介绍了S32K主要特性,S32K14x和S32K14xW系列高档架构框图和系列高档架构框图以及MCSXTE2BK142马达控制开发板主要特性，框图，电路图和材料清单.
S32K scalable family of AEC-Q100 qualified 32-bit Arm® Cortex®-M4F and Cortex-M0+ based MCUs targeted for general-purpose automotive and high-reliability industrial applications
S32K主要特性:
•Operating characteristics
Voltage range: 2.7 V to 5.5 V
Ambient temperature range: -40℃ to 105℃ forHSRUN mode,
-40℃ to 150℃ for RUN mode •Arm™ Cortex-M4F/M0+ core, 32-bit CPU
Supports up to 112 MHz frequency (HSRUN mode)with 1.25
Dhrystone MIPS per MHz
Arm Core based on the Armv7 Architecture andThumb?-2 ISA Integrated Digital Signal Processor (DSP)
Configurable Nested Vectored Interrupt Controller(NVIC)
Single Precision Floating Point Unit (FPU)
•Clock interfaces
4 - 40 MHz fast external oscillator (SOSC) with upto 50 MHz DC
external square input clock inexternal clock mode
48 MHz Fast Internal RC oscillator (FIRC)
8 MHz Slow Internal RC oscillator (SIRC)
128 kHz Low Power Oscillator (LPO)
Up to 112 MHz (HSRUN) System Phased LockLoop (SPLL)
Up to 20 MHz TCLK and 25 MHz SWD_CLK
32 kHz Real Time Counter external clock(RTC_CLKIN)•Power management
Low-power Arm Cortex-M4F/M0+ core withexcellent energy
efficiency
NXP S32K汽车通用和高可靠工业的可扩展微控制器开发方案
Power Management Controller (PMC) with multiplepower modes: HSRUN, RUN, STOP, VLPR, andVLPS. Note: CSEc (Security) or
EEPROM writes/erase will trigger error flags in HSRUN mode
(112MHz) because this use case is not allowed toexecute
simultaneously. The device will need toswitch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
Clock gating and low power operation supported onspecific
peripherals.
•Memory and memory interfaces
Up to 2 MB program flash memory with ECC
64 KB FlexNVM for data flash memory with ECCand EEPROM汽车缓冲器
emulation. Note: CSEc (Security) orEEPROM writes/erase will
trigger error flags inHSRUN mode (112 MHz) because this use
case isnot allowed to execute simultaneously. The devicewill need to switch to RUN mode (80 MHz) toexecute CSEc (Security) or
EEPROM writes/erase.
Up to 256 KB SRAM with ECC
Up to 4 KB of FlexRAM for use as SRAM orEEPROM emulation
Up to 4 KB Code cache to minimize performanceimpact of
memory access latencies
QuadSPI with HyperBus™ support
•Mixed-signal analog
Up to two 12-bit Analog-to-Digital Converter(ADC) with up to 32 channel analog inputs permodule
One Analog Comparator (CMP) with internal 8-bitDigital to Analog Converter (DAC)
•Debug functionality
Serial Wire JTAG Debug Port (SWJ-DP) combines
Debug Watchpoint and Trace (DWT)
Instrumentation Trace Macrocell (ITM)
Test Port Interface Unit (TPIU)
Flash Patch and Breakpoint (FPB) Unit
•Human-machine interface (HMI)
Up to 156 GPIO pins with interrupt functionality
Non-Maskable Interrupt (NMI)
•Communications interfaces
Up to three Low Power Universal Asynchronous
Receiver/Transmitter (LPUART/LIN) modules with DMA
supportand low power availability
Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
Up to three FlexCAN modules (with optional CAN-FD support)
FlexIO module for emulation of communication protocols and peripherals (UART, I 2C, SPI, I 2S, LIN, PWM, etc).
Up to one 10/100Mbps Ethernet with IEEE1588 support and two
Synchronous Audio Interface (SAI) modules.•Safety and Security
Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in theSHE (Secure Hardware Extension) Functional Specification. Note: CSEc
(Security) or EEPROM writes/erase willtrigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. Thedevice will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.128-bit Unique Identification (ID) number
Error-Correcting Code (ECC) on flash and SRAM memories System Memory Protection Unit (System MPU)Cyclic Redundancy Check (CRC) module Internal watchdog (WDOG)
External Watchdog monitor (EWM) module
•Timing and control
Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)
One 16-bit Low Power Timer (LPTMR) with flexible wake up control
Two Programmable Delay Blocks (PDB) with flexible trigger system One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels 32-bit Real Time Counter (RTC)•Package
32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP packageoptions •16 channel DMA with up to 63 request sources using DMAMUX
图1.S32K14x 和S32K14xW 系列高档架构框图
评估板MCSXTE2BK142
Motor control is one of the key applications for general purpose automotive MCU S32K14x and FOC is the most popular algorithmfor PMSM/BLDC motor control. In order to provide user a hardware platform for motor control quick prototype verification, the MCSXTE2BK142 motor control development board has been developed.
The MCSXTE2BK142 is designed to deliver a motor control HW solution to support 24 V automotive system which can be usedfor multiple applications such as Cooling Fan, Oil Pump, Water pump or Blower, and it is an out of box evaluation board forcustomer of automotive motor control
market.
图2.S32K11x 系列高档架构框图
To achieve the function features - the 12~36 V VBAT input is firstly connected an anti-reverse protection circuit and get outputof VIN, then converted by the DC-DC converter to get 7 V VPRE, and last get 5 V VDD output through two LDO regulators. The VIN is directly connected to 3-phase MOSFET high side power stage and GD3000 pre-diver to provide
power for motor control,the VDD is used by S32K142 MCU and TJA1043T CAN transceiver. For debug purpose, a SWD debug port is reserved forprogram download and debug. TTL UART communication interface is provided for FreeMASTER/MCAT communication and a5-pin connector is routed with TRIGMUX signal for FOC trigger monitor. Besides, a hall sensor and an encoder interface aredesigned for sensor based FOC motor control A signal conditional and PGA circuit are used to sample the 3-phase currents andback-electromotive force for Sensorless FOC. One CAN bus and one LIN bus as well as a high voltage PWM input interface
aredesigned for external connectivity extension, such as user motor control (rotation direction, speed) command input and motordiagnostic information feedback.
图3.MCSXTE2BK142马达控制开发板外形图
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