百兆以太⽹ICIP101G规格书
Single Port 10/100 MII/RMII/TP/Fiber
Fast Ethernet Transceiver
(85nm/Extreme Low PW, PWMT ? and EMIMT ?)
Features General Description
z 10/100Mbps IEEE 802.3/802.3u compliant Fast Ethernet transceiver
z Supports 100Base-TX/FX Media Interface z Supports MII/ RMII Interface
轮胎101网
z Supports Auto MDI/MDIX function z Power Management Tool
- APS, auto power saving while Link-off - 802.3az, protocol based power saving - WOL+, light traffic power saving - PWD, force-off power saving
- Supports MII with LPI for RX and TX - Supports RMII with LPI for RX
z Supports Base Line Wander compensation z Supports Interrupt function
z Built in synchronization FIFO to support jumbo frame size up to 12KB in MII mode (10KB in RMII 100Mbps mode)
z Supports MDC and MDIO to communicate with the MAC
z EMI Management Tool - F/W based control
- 4 levels for mapping the difference layout
length on the PCB
z Single 3.3V power supply z Built-in Vcore regulator
z DSP-based PHY Transceiver technology z System Debug Assistant Tool - 16 bit RX counter
- 9 bit RXError/CRC counter - Isolate MII/RMII - RX to TX Loopback - Loopback MII/RMII
z Using either 25MHz crystal/oscillator or 50MHz oscillator REF_CLK as clock source
z Built-in 49.9ohm resistors for simplifying BOM
z Flexible LED display z Process: 85nm
z
Package and operation temperature
IP101G: dice, 0~70℃
IP101GA: 48LQFP , 0~70℃ IP101GR: 32QFN, 0~70℃ IP101GRI: 32QFN, -40~85℃
IP101G is an IEEE 802.3/802.3u compliant single-port Fast Ethernet Transceiver for both 100Mbps and 10Mbps operations. It supports Auto MDI/MDIX function to simplify the network installation and reduce the system maintenance cost. To improve the system performance, IP101G provides a hardware interrupt pin to indicate the link, speed and duplex status change.
IP101G provides Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) to connect with different types of 10/100Mbps Media Access Controller (MAC). IP101G is designed to use category 5 unshielded twisted-pair cable or Fiber-Optic cables connecting to other LAN devices. A PECL interface is supported to connect with an external 100Base-FX
fiber optical transceiver. Except good performance, reliability, rich power saving method and extreme low operating current, IP101G provides a serial tool for system designers to complete their projects easily. They are System Debug Assistant Tool and EMI Management Tool.
IP101G is fabricated with advanced CMOS (85nm) technology and design is based on
IC Plus’s 5th Ethernet-PHY architecture, this feature makes IP101G consumes very low power. Such as in the full load operation (100Mbps_FDX), it only takes below 0.15W. IP101GA / IP101GR&IP101GRI are available in 48LQFP/32QFN, lead-free package.
* EMIMT: Patent under apply.
Application
■ NAS
■ Network Printers and Servers ■ IP Set-Top Box ■
IP/Smart TV
■ Game console
■ IP and Video Phone ■ PoE
■
Telecom Fiber device
Table Of Contents
Table Of Contents (2)
List of Figures (4)
List of Tables (5)
Revision History (6)
Features comparison between IP101G and IP101A/IP101AH (7)
Transmit and Receive Data Path Block Diagram (8)
1Pin diagram (9)
2Dice pad information (11)
3Pin description (12)
3.1IP101GA pin description (12)
3.2IP101GR/GRI pin description (16)
4Register Descriptions (19)
4.1Register Page mode Control Register (20)
4.2MII Registers (20)
4.3MMD Control Register (30)
4.4MMD Data Register (31)
4.5RX Counter Register (34)
4.6LED Pin Control Register (35)
4.7WOL+ Control Register (36)
4.8UTP PHY Specific Control Register (39)
4.9Digital IO Pin Control Register (39)
5Function Description (41)
5.1Major Functional Block Description (41)
5.1.1Transmission Description (41)
5.1.2MII and Management Control Interface (42)
5.1.3RMII Interface (43)
5.1.4Flexible Clock Source (45)
5.1.5Auto-Negotiation and Related Information (45) 5.1.6Auto-MDIX function (46)
5.2PHY Address Configuration (46)
5.3Power Management Tool (47)
5.3.1Auto Power Saving Mode (47)
5.3.2IEEE802.3az EEE (Energy Efficient Ethernet) (48) 5.3.3Force power down (48)
5.3.4WOL+ operation mode (48)
5.4LED Mode Configuration (52)
5.5LED Blink Timing (52)
5.6Repeater Mode (52)
5.7Interrupt (52)
5.8Miscellaneous (52)
5.9Serial Management Interface (53)
5.10Fiber Mode Setting (54)
5.11Jumbo Frame (54)
6Layout Guideline (55)
6.1General Layout Guideline (55)
6.2Twisted Pair recommendation (55)
7Electrical Characteristics (56)
7.1Absolute Maximum Rating (56)
7.2DC Characteristics (56)
7.3Crystal Specifications (57)
7.4AC Timing (58)
7.4.1Reset, Pin Latched-in, Clock and Power Source (58) 7.4.2MII Timing (59)
7.4.3RMII Timing (60)
7.4.4SMI Timing (61)
7.5Thermal Data (61)
8Order Information (62)
9Physical Dimensions (63)
9.148-PIN LQFP (63)
9.232-PIN QFN (64)