Write Leveling
For better signal integrity, DDR4 memory modules use fly-by topology for the com-mands, addresses, control signals, and clocks. Fly-by topology has benefits from the re-duced number of stubs and their length, but it also causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain t DQSS, t DSS, and t DSH specifications. Therefore, the device supports a write leveling feature to allow the controller to compensate for skew. This feature may not be required under some system conditions, provided the host can maintain the t DQSS, t DSS, and t DSH specifications.
The memory controller can use the write leveling feature and feedback from the device to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory con-troller involved in the leveling must have an adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay estab-lished though this exercise would ensure the t DQSS specification. Besides t DQSS, t DSS and t DSH specifications also need to be fulfilled. One way to achieve this is to combine the actual t DQSS in the application with an appropriate duty cycle and jitter on the DQS signals. Depending on the
actual t DQSS in the application, the actual values for t DQSL and t DQSH may have to be better than the absolute limits provided in the AC Timing Parameters section in order to satisfy t DSS and t DSH specifications. A conceptual tim-ing of this scheme is shown below.
Figure 22: Write Leveling Concept, Example 1
diff_DQS
diff_DQS
DQ diff_DQS
DQ T0T1T2T3T4T5CK_c
CK_t
T6T7
CK_c CK_t
Source Destination DQS driven by the controller during leveling mode must be terminated by the DRAM based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
All data bits carry the leveling feedback to the controller across the DRAM configura-tions: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently.Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to-clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)-to-clock relationship.
8Gb: x4, x8, x16 DDR4 SDRAM Write Leveling
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Notes:  1.Speed Bin table is only valid with DLL enabled.
2.When operating in 2t CK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable t CK range.
3.The programmed value of CWL must be less than or equal to the programmed value of CL.
4.This value applies to non-native t CK-CL-n RCD-n RP combinations.
5.When calculating t RC in clocks, values may not be used in a combination that violate t RAS or t RP .
6.This value exceeds the JEDEC requirement in order to allow additional flexibility, espe-cially for components. However, JEDEC SPD compliance may force modules to only sup-port the JEDEC defined value, please refer to the SPD documentation.
Refresh Parameters By Device Density
Table 165: Refresh Parameters by Device Density
Note:  1.Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine
if the devices support these options or requirements.
8Gb: x4, x8, x16 DDR4 SDRAM Refresh Parameters By Device Density