Device Configuration
Zynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication.The ZC702 board supports these configuration options:•PS Configuration: Quad SPI flash memory
•PS Configuration: Processor System Boot from SD Card (J64)•PL Configuration: USB JTAG configuration port (Digilent module)
•
PL Configuration: Platform cable header J2 and flying lead header J58 JTAG configuration ports
The JTAG configuration option is selected by setting SW16 as shown in Table 1-2 and SW10 as described in Programmable Logic JTAG Programming Options for PL configuration details. SW10 is c
allout 23 in Figure 1-2.Note:For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoC
Technical Reference Manual (UG585) [Ref 2].
Table 1-2:
Switch SW16 Configuration Option Settings Boot Mode
SW16.1
SW16.2
SW16.3
SW16.4
SW16.5
JTAG mode (1)
00000Independent JTAG mode 10000Quad SPI mode 00010SD mode
江淮汽车瑞鹰00110MIO configuration pin
MIO2
MIO3
MIO4
车亮MIO5
MIO6
Notes:
1.Default switch setting
Note:The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
documented in the DDR3 Design Guidelines section of the 7Series FPGAs Memory Interface Solutions v1.8 User Guide (UG586) [Ref 4]. The ZC702 DDR3 memory interface is a 40Ω impedance
implementation. Other memory interface details are available in UG586 and the 7Series FPGAs
Memory Resources User Guide (UG473) [Ref 5]. For more details, see the Micron MT41J256M8HX-15E data sheet at the Micron website [Ref 14].
Quad-SPI Flash Memory
[Figure 1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that can be used for configuration and data storage.•Part number: N25Q128A11ESF40G (Micron)•Supply voltage: 1.8V •Datapath width: 4 bits
•
Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 SoC are listed in Table 1-5.P3PS_DDR3_CAS_B G3CAS_B U66, U67, U68, U69R5PS_DDR3_RAS_B F3RAS_B U66, U67, U68, U69F3PS_DDR3_RESET_B N2RESET_B U66, U67, U68, U69P6PS_DDR3_CS_B H2CS_B U66, U67, U68, U69P5PS_DDR3_ODT G1
一汽大众速腾报价ODT
U66, U67, U68, U69
M7PS_VRN N7PS_VRP H7VTTVREF_PS P7
VTTVREF_PS
Table 1-5:Quad SPI Flash Memory Connections to the XC7Z020 SoC XC7Z020 (U1)
Schematic Net Name Quad-SPI Flash Memory (U41)MIO Select
Header Pin Name
Bank
Pin Number Pin Number Pin Name
PS_MIO6500A4QSPI_CLK 16C J26.2PS_MIO5500A3QSPI_IO31DQ3_HOLD_B
J25.2PS_MIO4
500
E4
QSPI_IO2
WP_B
J22.2
XC7Z020 (U1) Pin
Net Name
Component Memory
Pin Number
Pin Name
Reference Designator
上海通用汽车PS_MIO3
500F6QSPI_IO18DQ1J20.2PS_MIO2500A2QSPI_IO015DQ0J21.2PS_MIO1
500
A1
QSPI_CS_B
7
S_B
NA
Notes:
Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
XC7Z020 (U1)
Schematic Net Name Quad-SPI Flash Memory (U41)MIO Select
Header Pin Name
Bank
Pin Number Pin Number Pin Name
Table 1-7:USB Connector Pin Assignments and Signal Definitions Between J1 and U9
USB Connector
J1Net Name Description USB3320 (U9)
Pin Pin Name
1VBUS USB_VBUS_SEL+5V from host system22 2D_N USB_D_N Bidirectional differential serial data (N-side)19 3D_P USB_D_P Bidirectional differential serial data (P-side)18 5GND GND Signal ground33
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