ADC081500
ADC081500 High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter
Literature Number: SNAS319F
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ADC081500
High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter
General Description
The ADC081500 is a low power, high performance C MOS analog-to-digital converter that digitizes signals to 8 bits res-olution at sample rates up to 1.7 GSPS. Consuming a typical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating ar-chitecture, the fully differential comparator design, the inno-vative design of the internal sample-and-hold amplifier and the self-calibration scheme
enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.3 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset bi-nary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable output offset voltage between 0.8V and 1.2V.
The converter output has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to one-half the sample rate.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Indus-trial (-40°C ≤ T A≤ +85°C) temperature range.Features
■Internal Sample-and-Hold
■Single +1.9V ±0.1V Operation
■Choice of SDR or DDR output clocking
■Multiple ADC Synchronization Capability
■Guaranteed No Missing Codes
■Serial Interface for Extended Control
■Fine Adjustment of Input Full-Scale Range and Offset
■Duty Cycle Corrected Sample Clock
Key Specifications
■Resolution8 Bits ■Max Conversion Rate  1.5 GSPS (min)■Bit Error Rate10-18 (typ)■ENOB @ 748 MHz Input7.3 Bits (typ)■DNL±0.15 LSB (typ)■Power Consumption
■—Operating  1.2 W (typ)—Power Down Mode  3.5 mW (typ) Applications
■Direct RF Down Conversion
■Digital Oscilloscopes
■Satellite Set-top boxes
■Communications Systems
■Test Instrumentation
Block Diagram
20153153© 2009 National Semiconductor Corporation201531www.national C081500 High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter
Industrial Temperature Range
(-40°C < T A  < +85°C)
NS Package
ADC081500CIYB 128-Pin Exposed Pad LQFP
ADC081500DEV
Development Board
Pin Configuration
20153101
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
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A D C 0
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
3
OutV /SCLK
Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data
amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See Section 1.1.6. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data.See Section 1.3
4
OutEdge /DDR /SDATA
DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See Section 1.1.5.2).When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the (SDATA)input. See Section 1.2 for details on the extended control mode.
15DCLK_RST
DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outputs of multiple converters.See Section 1.5 for detailed description.
26PD
Power Down Pin. A logic high on the PD pin puts the device into the Power Down Mode.
30CAL
西雅特leon怎么样Calibration Cycle Initiate. A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the self calibration sequence. See Section 2.4.2.
14FSR/ECE
Full Scale Range Select and Extended Control Enable. In non-extended control mode, a logic low on this pin sets the full-scale differential input range to a reduced V IN  input level . A logic high on this pin sets the full-scale differential input range to a higher V IN  input level. See Converter Electrical Characteristics. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to V A /2. See Section 1.2 for information on the extended control mode.
127
CalDly /SCS
Calibration Delay and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See Section 1.1.1). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay).
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081500
Pin No.Symbol Equivalent Circuit Description
1819CLK+CLK-
LVDS Clock input pins for the ADC. The differential cl signal must coupled to these pins. The input si is sampled on the falling edge of CLK+. See Section 2
1110
V IN +V IN −
Analog signal inputs to the ADC. The differential full-s input range of this input is programmable using the FSR 14 in normal mode and the Input Full-Scale Voltage A register in the extended control mode. Refer to the V IN specification in the Converter Electrical Characteristic the full-scale input range in the normal mode. Refer to 1.4 for the full-scale input range in the extended contr mode.
7
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Common Mode Voltage. The voltage output at this pin required to be the common mode input voltage at V IN +V IN − coupling is used. This pin should be grounded coupling is used at the analog inp This pin is capable of sourcing or sinking 100 μA. See Section 2.2.
 31 
V BG
Bandgap output voltage capable of 100 μA source/sin
126CalRun
Calibration Running indication. This pin is at a logic hi when calibration is running.
32
R EXT
External bias resistor connection. Nominal value is 3.3Ohms (±0.1%) to ground. See Section 1.1.1.
3435Tdiode_P Tdiode_N
Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be used for die temperatu measurements, however no specified accuracy is imp or guaranteed. See Section 2.6.2.
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A D C 0
Pin No.Symbol Equivalent Circuit Description
83 84 85 86 89 90 91 92 93 94 95 96 100 101 102 103D7−
D7+
D6−
D6+
D5−
D5+
D4−
D4+
D3−
D3+
D2−
D2+
D1−
D1+
D0−
D0+
The LVDS Data Outputs that are not delayed in the output
demultiplexer. Compared with the Dd outputs, these
outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential
resistor.
104 105 106 107 111 112 113 114 115 116 117 118 122 123 124 125Dd7−
Dd7+
Dd6−
Dd6+
Dd5−
思域Dd5+
Dd4−
Dd4+
Dd3−
Dd3+
Dd2−
Dd2+
Dd1−
Dd1+
Dd0
Dd0
The LVDS Data Outputs that are delayed by one CLK cycle
in the output demultiplexer. Compared with the D outputs,
these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω
differential resistor.
79 80OR+
OR-
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside
the range ±V
IN
/2 as programmed by the FSR pin in non-
extended control mode or the Input Full-Scale Voltage
Adjust register setting in the extended control mode).
82 81DCLK+
DCLK-
Differential Clock outputs used to latch the output data.
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Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input
clock rate in SDR mode and at 1/4 the input clock rate in
the DDR mode. The DCLK outputs are not active during a
calibration cycle. The DCLK outputs are not active during a
calibration cycle, therefore this is not recommended as a
system clock.
2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128V
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Analog power supply pins. Bypass these pins to ground.
40, 51 ,62, 73, 88, 99,
110, 121V
DR
Output Driver power supply pins. Bypass these pins to DR
GND.
1, 6, 9, 12, 21, 24, 27,
41
GND Ground return for V A.
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